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gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion rev. 01 11 may 2004 product data 1. description the gtl1655 is a 16-bit bus transceiver that incorporates high-drive low-output-impedance (100 ma/12 w ) with lvttl-to-gtl/gtl+ and gtl/gtl+-to-lvttl logic level translation. the device is con?gured as two 8-bit transceivers that share a common clock and a master output enable pin, but also have individual latch timing and output enable signals. d-type ?ip-?ops and d-type latches enable three modes of data transfer; clocked, latched, or transparent. the gtl1655 provides the ideal interface between cards operating at lvttl levels and backplanes using gtl/gtl+ signal levels. the combination of reduced output swing, reduced input threshold levels and con?gurable edge control provides the higher speed operation of gtl/gtl+ backplanes. the gtl1655 can be used at gtl (v tt = 1.2 v, v ref = 0.8 v) or gtl+ (v tt = 1.5 v, v ref = 1.0 v) signalling levels. port a and the control inputs are compliant with lvttl signal levels and are 5 v tolerant. port b is designed to operate at gtl or gtl+ signal levels, with v ref providing the reference voltage input. the latch enable pins (nleab and nleba), the output enable pins (n oeab, n oeba) and the clock pin (cp) are used to control the data ?ow through the two 8-bit transceivers (n = 1 or 2). when nleab is set high, the device will operate in the transparent mode port a to port b. high-to-low transitions of nleab will latch a data independently of cp high or low (latched mode). low-to-high transitions of cp will clock a data to the b port if nleab is low (clocked mode). using the control pins nleba, n oeba and cp in the same way, data ?ow from port b to port a can be controlled. the oe pin can be used to disable all of the i/o pins. to optimize signal integrity, the gtl1655 features an adjustable edge rate control (v erc ). by adjusting v erc between gnd and v cc , a designer can adjust the port b edge rate to suit an applications load conditions. the gtl1655 permits true live insertion capability by incorporating: ? bias v cc , to pre-charge outputs and avoid disturbing active data during card insertion. ? i off to disable current ?ow through powered-off i/os. ? power-up 3-state, which ensures outputs are high-impedance during power-up, thus preventing bus contention issues. once v cc is above 1.5 v, the power-up 3-state circuit relinquishes control of the outputs to the oe pin. to ensure the outputs remain 3-state, the oe pin should be tied to v cc via a pull-up resistor.
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 2 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 2. features n combination of d-type latches and d-type ?ip-?ops for transceiver operation in clocked, latched or transparent mode n logic level translation between lvttl and gtl/gtl+ signals n high-drive low-output-impedance (100 ma/12 w ) on port b n con?gurable rise and fall times on port b n supports live insertion (i off , power-up 3-state, and bias v cc ) n bus hold on port a inputs n over voltage tolerance on port a n minimized switching noise through use of distributed v cc and gnd pins n available in tssop64 package n industrial temperature range ( - 40 cto+85 c) n esd protection u hbm eia/jesd22-a114-a exceeds 2000 v u cdm eia/jesd22-c101 exceeds 1000 v n latch-up eia/jeds78 exceeds 200 ma 3. quick reference data table 1: quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns symbol parameter conditions min typ max unit t plh propagation delay, nan to nbn v cc = 3.3 v; v erc = gnd; v tt = 1.5 v; v ref =1v - 3.9 - ns v cc = 3.3 v; v erc = gnd; v tt = 1.5 v; v ref =1v - 4.4 - ns propagation delay, nbn to nan v cc = 3.3 v - 2.6 - ns t phl propagation delay, nan to nbn v cc = 3.3 v; v erc = gnd; v tt = 1.5 v; v ref =1v - 3.1 - ns v cc = 3.3 v; v erc = gnd; v tt = 1.5 v; v ref =1v - 2.7 - ns propagation delay, nbn to nan v cc = 3.3 v - 4.2 - ns c i input capacitance (control pins) v i =v cc or gnd - 3 - pf c i/o i/o capacitance, port a v i =v cc or gnd - 7 - pf i/o capacitance, port b v i =v cc or gnd - 8 - pf
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 3 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 4. ordering information standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. 4.1 ordering options table 2: ordering information type number package name description version GTL1655DGG tssop64 plastic thin shrink small outline package; 64 leads; body width 6.1 mm sot646-1 table 3: part marking type number topside mark temperature range GTL1655DGG GTL1655DGG t amb = - 40 c to +85 c
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 4 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5. pinning information 5.1 pinning fig 1. tssop64 pin con?guration. GTL1655DGG 1oeab cp 1oeba 1leab v cc 1leba 1a1 v erc gnd gnd 1a2 1b1 1a3 1b2 gnd gnd 1a4 1b3 gnd 1b4 1a5 1b5 gnd gnd 1a6 1b6 1a7 1b7 v cc v cc 1a8 1b8 2a1 2b1 gnd gnd 2a2 2b2 2a3 2b3 gnd gnd 2a4 2b4 2a5 2b5 gnd v ref 2a6 2b6 gnd gnd 2a7 2b7 v cc 2b8 2a8 bias_v cc gnd 2leab 2oeab 2leba 2oeba 002aaa763 oe 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 5 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 5.2 pin description table 4: pin description symbol pin description 1 oeab 1 output enable 1a-to-1b (active-low) 1 oeba 2 output enable 1b-to-1a (active-low) v cc 3, 15, 28, 50 dc supply voltage 1a1 to 1a8 4, 6, 7, 9, 11, 13, 14, 16 data inputs/outputs port 1a gnd 5, 8, 10, 12, 18, 21, 24, 26, 30, 39, 44, 47, 53, 57, 60 ground (0 v) 2a1 to 2a8 17, 19, 20, 22, 23, 25, 27, 29 data inputs/outputs port 2a 2 oeab 31 output enable 2a-to-2b (active-low) 2 oeba 32 output enable 2b-to-2a (active-low) oe 33 output enable, all i/o pins (active-low) 2leba 34 latch enable 2b-to-2a 2leab 35 latch enable 2a-to-2b bias_v cc 36 bias supply voltage 2b8 to 2b1 37, 38, 40, 42, 43, 45, 46, 48 data inputs/outputs port 2b v ref 41 reference voltage 1b8 to 1b1 49, 51, 52, 54, 55, 56, 58, 59 data inputs/outputs port 1b v erc 61 edge-rate control voltage port b 1leba 62 latch enable 2b-to-2a 1leab 63 latch enable 1a-to-1b cp 64 clock input
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 6 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6. functional description fig 2. logic diagram. fig 3. logic diagram. 1d c1 cp 41 61 64 63 62 v ref v erc cp 1leab 1leba 2 1oeba 1 1oeab 33 oe 4 1a1 1d c1 cp to 7 other channels 59 1b1 002aaa764 1d c1 cp 41 61 64 35 34 v ref v erc cp 2leab 2leba 32 2oeba 31 2oeab 33 oe 17 2a1 1d c1 cp to 7 other channels 48 2b1 002aaa765
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 7 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 6.1 function table [1] a-to-b data ?ow is shown. b-to-a is similar, but uses oeba, leba, and cp. it is not recommended to set oeab and oeba low at the same time. x dont care h high voltage level l low voltage level z high-impedance off-state - low-to-high transition [2] output level before the indicated steady-state input conditions were established, provided that cp was high before leab went low. [3] output level before the indicated steady-state input conditions were established. table 5: function table see table note [1] . inputs output mode oeab leab cp port a port b hxxxz isolation l h x l l transparent l h x h h transparent ll - l l registered ll - h h registered llhxb0 [2] previous state lllxb0 [3] previous state table 6: output enable function table see table note [1] . inputs outputs oe oeab oeb a port a port b l l l active active l l h z active l h l active z l hhz z hxxzz table 7: port b edge-rate control (v erc ) function table see table note [1] . input v erc output port b edge-rate logic level nominal voltage hv cc slow l gnd fast
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 8 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 7. limiting values [1] stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under section 8 recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. [2] the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. [3] the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. table 8: limiting values in accordance with the absolute maximum rating system (iec 60134). see table note [1] and table note [2] symbol parameter conditions min max unit v cc dc supply voltage - 0.5 +4.6 v bias v cc bias supply voltage - 0.5 +4.6 v i ik input clamping diode current v i <0v - - 50 ma v i dc input voltage port a [3] - 0.5 +7.0 v port b; v erc , v ref [3] - 0.5 +4.6 v v o dc output voltage output in high or power-off state; port a - 0.5 +7.0 v output in high or power-off state; port b - 0.5 +4.6 v i ol(d) dc low-level diode output current port a - 48 ma port b - 200 ma i oh(d) dc high-level diode output current port a - 48 ma t stg storage temperature - 65 +150 c
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 9 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 8. recommended operating conditions table 9: recommended operating conditions symbol parameter conditions min max unit bias v cc dc supply voltage 3.0 3.6 v v tt termination voltage gtl 1.14 1.26 v gtl+ 1.35 1.65 v v ref gtl reference voltage gtl 0.74 0.87 v gtl+ 0.87 1.10 v v i input voltage port b 0 v tt v except port b 0 5.5 v v ih high-level input voltage port b v ref +50mv - v except port b 2.0 - v v erc v cc - 0.6 - v v il low-level input voltage port b - v ref - 50 mv v except port b - 0.8 v v erc - 0.6 v | i ik | input clamp current - 18 ma i oh high-level output current port a - - 24 ma i ol low-level output current port a - 24 ma port b - 100 ma d t/ d v cc power-up ramp rate 200 - m s/v t amb operating ambient temperature - 40 85 c
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 10 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 9. static characteristics table 10: dc characteristics t amb = - 40 c to +85 c; values otherwise stated v ref =1v; v tt = 1.5 v. symbol parameter conditions min typ [1] max unit v ik input clamp voltage v cc = 3.0 v; i ik =19ma - - - 1.2 v v oh high-level output voltage port a v cc = 3.0 v to 3.6 v; i oh = - 100 m a v cc - 0.2 - - v v cc = 3.0 v; i oh = - 12 ma 2.4 - - v v cc = 3.0 v; i oh = - 24 ma 2.2 - - v v ol low-level output voltage port a v cc = 3.0 to 3.6 v; i ol = 100 m a - - 0.2 v v cc = 3.0 v; i ol =12ma - - 0.4 v v cc = 3.0 v; i ol =24ma - - 0.55 v port b v cc = 3.0 v; i ol =40ma - - 0.2 v v cc = 3.0 v; i ol =80ma - - 0.4 v v cc = 3.0 v; i ol = 100 ma - - 0.5 v i i input leakage current control pins v cc = 3.6 v; v i =v cc or gnd -- 10 m a port b v cc = 3.6 v; v i =v tt or gnd -- 10 m a i off output off current port a + control pin v cc =0v; v o = 0 v to 3.6 v -- 100 m a port b v cc =0v; v o = 0 v to 1.5 v -- 300 m a i hold bus hold current, a outputs port a v cc = 3.0 v; v i = 0.8 v 75 - - m a v cc = 3.0 v; v i = 2.0 v - 75 - - m a overdrive current port a v cc = 3.6 v; v i =0vtov cc [2] -- 500 m a i ozh high off-state output current port b v cc = 3.6 v; v o = 1.5 v --10 m a i ozl low off-state output current port b v cc = 3.6 v; v o = 0.4 v -- - 10 m a i oz off-state output current port a v cc = 3.6 v; v o =v cc or gnd [3] --10 m a i ozpu power-up 3-state output current v cc = 0 to 3.6 v; v o = 0.5 v to 3 v; oe = low -- 50 m a i ozpd power-down 3-state output current v cc = 3.6 to 0 v; v o = 0.5 v to 3 v; oe = low -- 50 m a
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 11 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. [1] all typical values are measured at v cc = 3.3 v and t amb =25 c. [2] this is the bus-hold maximum dynamic current. it is the minimum overdrive current required to switch the input from one stat e to another. [3] for i/o ports, this parameter i oz includes the input leakage current. [4] this is the increase in supply current for each input that is at the speci?ed ttl voltage level rather than v cc or gnd. i cc quiescent supply current outputs high v cc = 3.6 v; v i =v cc or gnd; i o =0ma --45ma outputs low v cc = 3.6 v; v i =v cc or gnd; i o =0ma --45ma disabled v cc = 3.6 v; v i =v cc or gnd; i o =0ma --45ma d i cc additional quiescent supply current per input pin; except port b v cc = 3.6 v; one input at v cc - 0.6 v; port a or control inputs at v cc or gn d [4] - 0.1 - ma c i input capacitance control pins v cc = 3.6 v; v i =v cc or 0 - 35pf c io i/o capacitance port a v cc = 3.6 v; v i =v cc or 0 - 78pf port b v cc = 3.6 v; v i =v cc or 0 - 8 10 pf table 10: dc characteristics continued t amb = - 40 c to +85 c; values otherwise stated v ref =1v; v tt = 1.5 v. symbol parameter conditions min typ [1] max unit table 11: live insertion characteristics t amb = - 40 c to +85 c symbol parameter conditions min typ max unit i cc (bias v cc ) supply current v cc = 0 v to 3.0 v; v (port b) = 0 to 1.2 v; v i (bias v cc ) = 3.0 v to 3.6 v --5ma v cc = 3.0 v to 3.6 v; v (port b )=0to1.2v; v i (bias v cc ) = 3.0 v to 3.6 v --10 m a v o output voltage port b v cc =0v; v i (bias v cc ) = 3.3 v 1 - 1.2 v i o output current port b v cc = 0 v; v (port b) = 0.4 v; v i (bias v cc )=3vto3.6v - 1- - m a v cc =0vto3.6v; oe = 3.3 v; v (port b) = 0 v to 1.5 v - - 300 m a v cc =0vto1.5v; oe = 0 v to 3.3 v; v (port b) = 0 v to 1.5 v - - 300 m a
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 12 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10. dynamic characteristics table 12: timing requirements over recommended supply voltage v tt = 1.2 v; v ref = 0.8 v and v erc =v cc or gnd for gtl (unless otherwise noted; see figures 15 and 16 ). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit t w pulse duration cp high or low; see figures 4 and 5 3.0 - - ns le high; see figures 6 and 7 3.0 - - ns t su set-up time data before cp - ; see figures 4 and 5 2.7 - - ns data before le ; see figures 6 and 7 2.8 - - ns t h hold time data after cp - ; see figures 4 and 5 0.4 - - ns data after le ; see figures 6 and 7 1.2 - - ns table 13: port a to port b switching v tt = 1.2 v; v ref = 0.8 v and v erc =v cc or gnd for gtl (see figure 16 ). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit t plh a to b oeab = oe=0v; leab = 3 v v erc =v cc ; see figure 10 3.1 5.3 6.2 ns t phl 2.2 3.8 6.2 ns t plh cp to b oeab = oe=0v; leab = 0 v v erc =v cc ; see figure 4 3.4 5.9 7.2 ns t phl 2.4 4.1 6.0 ns t plh leab to b oeab = oe=0v; cp = 0 or 3 v v erc =v cc ; see figure 8 3.3 5.7 7.0 ns t phl 2.6 4.6 6.8 ns t plh oeab or oe to b leab = 3.0 v; port a = 0 v v erc =v cc ; see figure 12 2.7 5.3 6.5 ns t phl 2.5 3.9 6.4 ns t plh a to b oeab = oe=0v; leab = 3 v v erc = gnd; see figure 10 2.3 4.4 5.3 ns t phl 1.7 2.7 4.4 ns t plh cp to b oeab = oe=0v; leab = 0 v v erc = gnd; see figure 4 2.7 5.2 6.1 ns t phl 1.8 3.7 5.3 ns t plh leab to b oeab = oe=0v; cp = 0 or 3 v v erc = gnd; see figure 8 2.5 4.8 6.5 ns t phl 2.0 3.6 5.3 ns t plh oeab or oe to b leab = 3.0 v; port a = 0 v v erc = gnd; see figure 12 2.0 4.8 6.2 ns t phl 2.0 3.1 4.9 ns d v/ d t output slew rate 0.6 v to 1.0 v v erc =v cc - - 1 v/ns v erc = gnd - - 1 v/ns t sk(o) output edge skew measured at v ref --1ns
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 13 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 14: port b to port a switching v tt = 1.2 v; v ref = 0.8 v for gtl (see figure 15 ). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit f max maximum frequency 160 - - mhz t plh b to a oeba = oe=0v; leba = 3 v see figure 11 1.8 2.6 4.9 ns t phl 2.3 4.2 5.3 ns t plh cp to a oeba = oe=0v; leba = 0 v see figure 5 1.5 3.1 4.4 ns t phl 1.5 3.7 4.6 ns t plh leba to a oeba = oe = 0 v see figure 9 1.3 2.7 4.0 ns t phl 1.4 3.1 3.9 ns t pzl oeba or oe to a leba = 3.0 v; port b = 0 v see figure 13 1.3 3.1 5.1 ns t plz 1.7 2.8 6.1 ns t pzh leba = 3 v; port b = v tt see figure 14 1.3 3.3 5.1 ns t phz 1.7 3.3 6.1 ns t sk(o) output edge skew measured at 1.5 v - - 1 ns
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 14 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. table 15: timing requirements over recommended supply voltage v tt = 1.5 v; v ref = 1 v and v erc =v cc or gnd for gtl+ (unless otherwise noted). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit t w pulse duration cp high or low; see figures 4 and 5 3.0 - - ns le high; see figures 6 and 7 3.0 - - ns t su set-up time data before cp - ; see figures 4 and 5 2.7 - - ns data before le ; see figures 6 and 7 2.8 - - ns t h hold time data after cp - ; see figures 4 and 5 0.4 - - ns data after le ; see figures 6 and 7 1.2 - - ns table 16: port a to port b switching v tt = 1.5 v; v ref = 1 v and v erc =v cc or gnd for gtl+ (see figures 15 and 16 ). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit t plh a to b oeab = oe=0v; leab = 3 v v erc =v cc ; see figure 10 3.0 4.7 6.1 ns t phl 2.3 4.4 6.5 ns t plh cp to b oeab = oe=0v; leab = 0 v v erc =v cc ; see figure 4 3.3 5.3 7.0 ns t phl 2.7 4.7 6.2 ns t plh leab to b oeab = oe=0v; cp = 0 or 3 v v erc =v cc ; see figure 8 3.2 5.2 6.8 ns t phl 2.8 5.2 7.1 ns t plh oeab or oe to b leab = 3.0 v; port a = 0 v v erc =v cc ; see figure 12 3.2 4.8 6.5 ns t phl 2.6 4.6 6.6 ns t plh a to b oeab = oe=0v; leab = 3 v v erc = gnd; see figure 10 2.3 3.9 5.2 ns t phl 1.7 3.1 4.5 ns t plh cp to b oeab = oe=0v; leab = 0 v v erc = gnd; see figure 4 2.5 4.8 6.0 ns t phl 1.9 4.1 5.4 ns t plh leab to b oeab = oe=0v; cp = 0 or 3 v v erc = gnd; see figure 8 2.5 4.3 6.5 ns t phl 2.1 4.0 5.4 ns t plh oeab or oe to b leab = 3.0 v; port a = 0 v v erc = gnd; see figure 12 2.1 4.4 6.1 ns t phl 2.0 3.4 5.0 ns d v/ d t output slew rate 0.6 v to 1.3 v v erc =v cc - - 1 v/ns v erc = gnd - - 1 v/ns t sk(o) output edge skew measured at v ref --1ns
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 15 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 10.1 ac waveforms table 17: port b to port a switching v tt = 1.5 v; v ref = 1 v for gtl+ (see figures 15 and 16 ). t amb = - 40 c to +85 c. symbol parameter conditions min typ max unit f max maximum frequency 160 - - mhz t plh b to a oeba = oe=0v; leba = 3 v see figure 11 1.8 2.6 4.9 ns t phl 2.3 4.2 5.3 ns t plh cp to a oeba = oe=0v; leba = 0 v see figure 5 1.5 3.1 4.4 ns t phl 1.5 3.7 4.6 ns t plh leba to a oeba = oe = 0 v see figure 9 1.3 2.7 4.0 ns t phl 1.4 3.1 3.9 ns t pzl oeba or oe to a leba = 3.0 v; port b = 0 v see figure 13 1.3 3.1 5.1 ns t plz 1.7 2.8 6.1 ns t pzh leba = 3 v; port b = v tt see figure 14 1.3 3.3 5.1 ns t phz 1.7 3.3 6.1 ns t sk(o) output edge skew measured at 1.5 v - - 1 ns test condition: oeab = oe = 0 v test condition: oeab = oe=0v; leba = 0 v fig 4. cp to b timing. fig 5. cp to a timing. test condition: oeab = oe = 0 v test condition: oeab = oe=0v fig 6. leab set-up and hold times. fig 7. leba set-up and hold times. 002aaa766 3.0 v 0 v v tt v ol t plh t phl v ref v ref 1.5 v 1.5 v 1.5 v t w cp input port b output t w 1.5 v 1.5 v 1.5 v t su t h t su port a input t h 1.5 v 0 v 3.0 v 002aaa767 3.0 v 0 v v oh v ol t plh t phl 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v t w cp input port a output t w v ref t su t h t su port b input t h v ref 0 v v tt v ref v ref 002aaa768 3.0 v 0 v 1.5 v 1.5 v 1.5 v t w leab input 1.5 v 1.5 v 1.5 v t su t h t su port a input t h 1.5 v 0 v 3.0 v 002aaa769 3.0 v 0 v 1.5 v 1.5 v 1.5 v t w leba input v ref t su t h t su port b input t h v ref 0 v v tt v ref v ref
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 16 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. test condition: oeab = oe = 0 v; cp = 0 v or 3 v test condition: oeab = oe=0v; cp=0vor3v fig 8. leab to b propagation delay. fig 9. leba to a propagation delay. test conditions: oeab = oe = 0 v; leab = 3 v test conditions: oeba = oe=0v; leba = 3 v fig 10. a to b propagation delay. fig 11. b to a propagation delay. test conditions: leab = 3 v; port a = 0 v test conditions: leba = 3 v; port b = 0 v fig 12. oe or oeab to b propagation delay. fig 13. oe or oeb a to a propagation delay. test conditions: leba = 3 v; port b = v tt fig 14. oe or oeb a to a propagation delay. 002aaa770 3.0 v 0 v v tt v ol t plh t phl v ref v ref 1.5 v 1.5 v 1.5 v t w leab input port b output 002aaa771 3.0 v 0 v v oh v ol t plh t phl 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v t w leba input port a output 002aaa772 3.0 v 0 v v tt v ol t plh t phl v ref v ref 1.5 v 1.5 v port a input port b input 002aaa773 v tt 0 v v oh v ol t plh t phl 1.5 v 1.5 v v ref v ref port b input port a input 002aaa774 3.0 v 0 v v tt v ol t phl t plh v ref v ref 1.5 v 1.5 v oe or oeab input port b output 002aaa775 3.0 v 0 v 3.0 v v ol t pzl t plz v ol + 0.3 v 1.5 v 1.5 v 1.5 v oe or oeba input port a output 002aaa776 3.0 v 0 v v oh 0 v t pzh t phz v oh - 0.3 v 1.5 v 1.5 v 1.5 v oe or oeba input port a output
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 17 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 11. test information r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 15. load circuitry for port a output switching times. r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator. fig 16. load circuitry for port b output switching times. pulse generator d.u.t. v o c l 50 pf r l 500 w 6 v open gnd s1 002aaa777 r l 500 w r t v i v cc pulse generator d.u.t. v o c l 30 pf r l 12.5 w 002aaa778 r t v i v cc v tt
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 18 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 12. package outline fig 17. tssop64 package outline (sot646-1). unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot646-1 00-08-21 03-02-18 w m q a a 1 a 2 d l p detail x e z e c l x (a ) 3 0.25 y b p h e 1.05 0.85 0.27 0.17 0.2 0.1 17.1 16.9 6.2 6.0 0.5 1 0.2 8.3 7.9 0.89 0.61 0.08 0.75 0.45 v m a a tssop64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm sot646-1 a max. 1.2 0 2.5 5 mm scale 1 64 pin 1 index 32 33 mo-153
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 19 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. 13. soldering 13.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for ?ne pitch smds. in these situations re?ow soldering is recommended. in these situations re?ow soldering is recommended. 13.2 re?ow soldering re?ow soldering requires solder paste (a suspension of ?ne solder particles, ?ux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. several methods exist for re?owing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical re?ow peak temperatures range from 215 to 270 c depending on solder paste material. the top-surface temperature of the packages should preferably be kept: ? below 225 c (snpb process) or below 245 c (pb-free process) C for all bga, htsson..t and ssop..t packages C for packages with a thickness 3 2.5 mm C for packages with a thickness < 2.5 mm and a volume 3 350 mm 3 so called thick/large packages. ? below 240 c (snpb process) or below 260 c (pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm 3 so called small/thin packages. moisture sensitivity precautions, as indicated on packing, must be respected at all times. 13.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was speci?cally developed. if wave soldering is used the following conditions must be observed for optimal results: ? use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 20 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. ? for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. ? for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be ?xed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 c or 265 c, depending on solder material applied, snpb or pb-free respectively. a mildly-activated ?ux will eliminate the need for removal of corrosive residues in most applications. 13.4 manual soldering fix the component by ?rst soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the ?at part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 13.5 package related soldering information [1] for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales of?ce. [2] all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . table 18: suitability of surface mount ic packages for wave and re?ow soldering methods package [1] soldering method wave re?ow [2] bga, htsson..t [3] , lbga, lfbga, sqfp, ssop..t [3] , tfbga, uson, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hso, hsop, hsqfp, hsson, htqfp, htssop, hvqfn, hvson, sms not suitable [4] suitable plcc [5] , so, soj suitable suitable lqfp, qfp, tqfp not recommended [5][6] suitable ssop, tssop, vso, vssop not recommended [7] suitable cwqccn..l [8] , pmfp [9] , wqccn..l [8] not suitable not suitable
philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion product data rev. 01 11 may 2004 21 of 23 9397 750 12936 ? koninklijke philips electronics n.v. 2004. all rights reserved. [3] these transparent plastic packages are extremely sensitive to re?ow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared re?ow soldering with peak temperature exceeding 217 c 10 c measured in the atmosphere of the re?ow oven. the package body peak temperature must be kept as low as possible. [4] these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. [5] if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. [6] wave soldering is suitable for lqfp, qfp and tqfp packages with a pitch (e) larger than 0.8 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. [7] wave soldering is suitable for ssop, tssop, vso and vsop packages with a pitch (e) equal to or larger than 0.65 mm; it is de?nitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. [8] image sensor packages in principle should not be soldered. they are mounted in sockets or delivered pre-mounted on ?ex foil. however, the image sensor package can be mounted by the client on a ?ex foil by using a hot bar soldering process. the appropriate soldering pro?le can be provided on request. [9] hot bar soldering or manual soldering is suitable for pmfp packages. 14. revision history table 19: revision history rev date cpcn description 01 20040511 - product data (9397 750 12936).
9397 750 12936 philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion ? koninklijke philips electronics n.v. 2004. all rights reserved. product data rev. 01 11 may 2004 22 of 23 contact information for additional information, please visit http://www.semiconductors.philips.com . for sales of?ce addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com . fax: +31 40 27 24825 15. data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. de?nitions short-form speci?cation the data in a short-form speci?cation is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values de?nition limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. 17. disclaimers life support these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change noti?cation (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise speci?ed. level data sheet status [1] product status [2][3] de?nition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn).
? koninklijke philips electronics n.v. 2004. printed in the u.s.a. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. date of release: 11 may 2004 document order number: 9397 750 12936 contents philips semiconductors gtl1655 16-bit lvttl-to-gtl/gtl+ bus transceiver with live insertion 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 functional description . . . . . . . . . . . . . . . . . . . 6 6.1 function table . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 recommended operating conditions. . . . . . . . 9 9 static characteristics. . . . . . . . . . . . . . . . . . . . 10 10 dynamic characteristics . . . . . . . . . . . . . . . . . 12 10.1 ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 15 11 test information . . . . . . . . . . . . . . . . . . . . . . . . 17 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 13 soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.1 introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13.2 re?ow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 13.4 manual soldering . . . . . . . . . . . . . . . . . . . . . . 20 13.5 package related soldering information . . . . . . 20 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 15 data sheet status . . . . . . . . . . . . . . . . . . . . . . . 22 16 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 17 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

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